1. Field of the Invention
The present invention generally relates to digital communications and, more particularly, to a method of synchronization for asynchronous communication when data is transmitted using one clock signal and then must be synchronized with another clock signal of the same nominal frequency at the receiving station. The technique according to the invention allows the use of asynchronous communication where synchronous communication had previously been required.
2. Description of the Prior Art
The problem addressed by the present invention is the special case of transmitting data between two systems working at the same nominal frequency. Moreover, the invention is intended for use in high speed data transmission requiring the avoidance of clocks with frequencies higher than the data bit rate.
A common synchronization technique used in the prior art is to synchronize received data to a local clock signal using a D-type flip-flop. This technique, however, produces errors whenever setup and hold time specifications for the flip-flop are violated. Another technique commonly used in the prior art is to use a first-in, first-out (FIFO) register to provide the necessary elasticity required to properly synchronize the received data to the local clock signal. The use of a FIFO register, however, results in a certain ripple through delay and initialization problems associated with such a register. Further, some synchronization techniques are dependent on certain hardware characteristics. One such characteristic is a metastability problem which shows up whenever a flip-flop is clocked without a guaranteed setup and/or hold time, which is exactly what happens when efforts are made to synchronize the data with a new clock.
Specific examples of prior art synchronization systems include U.S. Pat. Nos. 3,825,683 to Pitroda et al. and 4,119,796 Jones. These, however, require a clock signal with a frequency which is four times the nominal data bit rate. U.S. Pat. No. 4,525,849 to Wolf describes a synchronization technique which is aimed at data transmission between a computer and peripherals that may run at different speeds. This design uses an elaborate buffer memory and does not guarantee a fixed delay for a retransmitted signal. U.S. Pat. Nos. 3,887,769 to Cichetti and 4,070,630 to Hepworth ignore the metastability phenomenon and do not condition or guard the two free running clocks before using them in the synchronization circuitry. Therefore, the bit error rate in either design will depend on the characteristics of the hardware.